Because of their relative ease of fabrication on large area substrates thin film transistors (TFTs) have been actively studied for use in driving individual pixels in large area displays, such as liquid crystal displays. The TFTs generally comprise spaced apart source and drain electrodes, held at different potentials, and electrically interconnected by a semiconductor material which forms a channel therebetween. Current flow between these electrodes, is controlled by the application of a voltage to a gate electrode, which is adjacent a portion of the semiconductor material and is insulated therefrom. The gate field acts to invert or accumulate a portion of the semiconductor material, allowing current to flow therethrough from the source to the drain.
Amorphous silicon technology was initially developed primarily for photovoltaics but recently the microelectronic applications therefor have become more and more important. They are ideally suited for use in large area arrays because of the low deposition temperatures involved in their fabrication and the availability of large area deposition and lithographic equipment. Although amorphous silicon has been the most promising semiconductor material for TFTs, other materials such as Ge, GaAs, CdS, polycrystalline silicon and microcrystalline silicon have been found to be satisfactory. A shortcoming of amorphous silicon is its relatively low electron mobility which limits the operating speed of these transistors. In order to improve the operating speed and to increase the output current, reduction of the channel length L is very important because the transit time of electrons across a channel is proportional to L.sup.2 and the output current is inversely proportional to the channel length (1/L). Typically, lithographically produced TFTs have channel lengths of about 10 .mu.m. Of course, the channel length could possibly be decreased substantially by using critical lithographic techniques developed for VLSI fabrication, but this solution is very costly and is impractical over the large areas contemplated. In fact, it is likely that a one micron feature size cannot be accurately maintained over very large areas.
In spite of the fact that the amorphous silicon electron band mobility is 10 to 20 cm.sup.2 /volt-sec, these TFTs operate with a field effect mobility of around 1 cm.sup.2 /volt-sec. This is due to the fact that traps in the form of localized tail states allow only a small fraction (about 10 to 20%) of the charge induced into the channel of these TFTs to become mobile carriers. For a 10 .mu.m feature size and gate width-to-length ratio of 10, one may expect output currents on the order of 10 to 50 .mu.amp and a transit time of approximately 100 nsec for drive voltages in the range of 10 to 20 volts. In practice switching speeds also will be reduced by circuit capacitances. Improved current drive capabilities necessitate shorter channel lengths.
One form of short channel thin film transistor is to be found in U.S. Pat. No. 4,547,789 comprising a mesa-like formation including vertically stacked source and drain regions separated by an insulating layer. A plurality of thin layers including a semiconductor layer, a gate dielectric layer and a gate electrode layer overlie the mesa and extend between the source and drain regions along its side walls. Two short current conduction channels (one on either side of the mesa) are thus formed. The thickness of the insulating layer between the source and drain regions determines the current conduction channel length through the side wall semiconductor layer. In this matter, the channel length can be very accurately controlled without critical lithography.
Several other short channel TFT structures are disclosed in an article entitled "Vertical-Type a-Si:H Field-Effect Transistors" by Uchida et al. of Tokyo Institute of Technology, published in Materials Research Society Symposium Proceedings, Vol. 33 (1984), at pages 287-292. In each described structure current flow is controlled from source to drain electrode layers disposed in a stack, by means of thin sidewall gate electrode layers controlling a sidewall semiconductor layer.
In the devices of both the '789 patent and the Uchida et al article, very narrow channels are formed in the sidewall regions between the source and drain electrode, at the semiconductor/gate dielectric interface. The current flow is perpendicular to the direction of the gate field, as in conventional TFTs. These short channel devices have low ON/OFF ratios at moderate source to drain voltage and therefore have limited voltage handling capabilities.
It is the object of the present invention to provide a unique short channel thin film transistor having a unique structure wherein the gate electrode is located, relative to the source electrode, on the side remote from the drain electrode and wherein current flow is parallel to the gate field over the majority of the device.
It is another object of the present invention to provide a vertical thin film transistor whose effective channel length is much less than any minimum lithographic feature size used in its fabrication.
It is a further object of this invention to provide a vertical thin film transistor having barrier means between the source electrode and the semiconductor channel layer which barrier means is controlled by the gate electrode, so as to improve the ON/OFF current ratio of the device and to improve output saturation characteristics.
A still further object of this invention is to form the source electrode as a series of stripes or fingers electrically connected in parallel so as to increase the effective channel area.